1. Field of the Invention
The present invention relates to a semiconductor device and a method for testing the semiconductor device, and more specifically, to a semiconductor device having plural clock domains whose operating frequencies are different from one another and a method for testing the semiconductor device.
2. Description of Related Art
In a field of scan path test of the semiconductor device, with microfabrication technique of the semiconductor process, it has become that sufficient quality can no longer be maintained only with the single stuck-at fault model that has been used for a long time.
In order to maintain sufficient quality of the semiconductor device, it has become indispensable to consider also transition delay fault and path delay fault. Moreover, it has become necessary to consider new faults, such as bridge fault and SDQM (Statistical Delay Quality Model).
Although the use of these additional tests makes it possible to secure the quality, on the other hand, a test cost has considerably increased.
Reduction of the test cost is an essential problem. As solution means, with execution of a multiple parallel test, necessity of performing the single stuck-at test and a delay test at an actual operating frequency with fewer test terminals has increased.
In relation to the above, Patent Document (Japanese Patent Application Laid Open No. 2006-38743) discloses description related to a semiconductor integrated circuit device and a test device of it. The related technology will be explained.
FIG. 1 is a schematic diagram for explaining configurations of the semiconductor device (LSI: Large Scale Integrated circuit) according to the related technology disclosed in the Patent Document and of a test board 1 for performing the delay test by a scan path method on the semiconductor device.
The test board 1 has a clock oscillator 3. The semiconductor device 2 has a PLL (Phase-Locked Loop) circuit 4, a pulse generation circuit 5, a scan clock signal input part SCK, a multiplexer circuit 6, and a scan path test circuit 7. The pulse generation circuit 5 has a pulse number control circuit 8 and a pulse selection circuit 9.
The pulse generation circuit 5 generates a clock SCK0 for the delay test whose pulse number is based on the scan clock SCK. The scan path test circuit 7 tests the integrated circuit of the semiconductor device with the clock SCK0 for the delay test.
In an example of FIG. 1, even if the test board 1 is capable of generating only a clock signal whose frequency is low, a clock signal of a high frequency required for the delay test can be generated in the inside of an LSI 2.
A capture operation of the scan test will be explained. The scan clock signal input part SCK is inputted with the number of clock pulses required for the capture operation of the scan path test circuit 7.
As many pulses of the clock SCK0 for the delay test as the clock pulses inputted from the scan clock SCK are extracted from the PLL clock that was multiplied by a PLL 4 using the pulse generation circuit 5. Subsequently, the capture operation of the scan path test circuit 7 is performed using the clock SCK0 for the delay test.
Therefore, the delay test based on the PLL clock operating frequency is possible regardless of a frequency of the scan clock SCK.
Functions of circuits used in the semiconductor integrated circuit device of FIG. 1 will be explained below.
The clock oscillator 3 is a circuit of generating and outputting a test clock signal of a predetermined cycle. The test clock signal that the clock oscillator 3 generates is outputted toward the LSI 2.
The PLL 4 is a circuit that is inputted with the test clock generated by the clock oscillator 3, multiplies its frequency, shapes its waveform, does others, and subsequently outputs it as a PLL clock signal (PLL_CLK).
FIG. 2 is a circuit diagram for explaining a detailed configuration of the pulse generation circuit 5. The pulse generation circuit 5 has the pulse number control circuit 8 and the pulse selection circuit 9. Operations of the pulse generation circuit 5 will be explained by dividing them into operations of the pulse number control circuit 8 and operations of the pulse selection circuit 9.
The pulse number control circuit 8 is a circuit that is inputted with a Control signal and a scan clock signal SCK, and memorizes the number of the clock pulses that the pulse generation circuit 5 should output. The pulse number control circuit 8 counts the pulse number of the scan clock signal SCK in response to the Control signal that is a control signal from the outside.
The pulse selection circuit 9 is a circuit that extracts a clock signal SCK0 for the delay test from the PLL clock signal (PLL_CLK) multiplied by the PLL 4. In response to START_PULSE that is the control signal inputted from the outside, the pulse selection circuit 9 starts to output the clock SCK0 for the delay test, and selects and outputs the clock signal latched in the pulse number control circuit 8. For example, after START_PULSE changed from 0 to 1, it outputs as many clock SCK0 for the delay test as the number of pulses having been set up in the pulse number control circuit 8.
A multiplexer 6 is a selection circuit of two inputs and one output. In the figure, the multiplexer 6 is inputted with the scan clock SCK and the clock SCK0 for the delay test, selects either of them, and outputs it toward the scan path test circuit 7. Incidentally, the multiplexer 6 switches the signal that is selected in response to the control signal inputted from the outside.
FIG. 3 is a timing chart in the case of generating 2PULSE in the pulse generation circuit 5. Using FIG. 3, an operation of the pulse generation circuit in the delay test using a PLL clock will be explained.
When generating the desired clock SCK0 for the delay test, first, the PLL 4 is initialized. Then, the PLL 4 multiples the test clock inputted from the clock oscillator 3 to generate a fast clock PLL_CLK.
Subsequently, the control signal of the pulse generation circuit 5 is changed into “0” from “1,” changing the operational mode of the LSI 2 to a counter mode ((a) in FIG. 3). Subsequently, a pulse of the scan clock SCK is inputted and a shift operation is performed by the pulse number control circuit 8.
Thereby, the number of inputted pulses is counted and is set up in the pulse number control circuit 8 ((b) in FIG. 3). That is, PULSE_ON becomes “1” following a first pulse of the scan clock SCK, and 2PULSE becomes “1” following a second pulse of the scan pulse clock SCK. The number of pulses being set up becomes the pulse number of the clock SCK0 for the delay test.